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PILATUS ProjectContact: christian.broennimann@psi.ch The PILATUS detector (pixel apparatus for the SLS) is a novel type of a x-ray detector, which has been developed at the Paul Scherrer Institut (PSI) for the Swiss Light Source (SLS). PILATUS detectors are two-dimensional hybrid pixel array detectors, which operate in single-photon counting mode. A hybrid pixel that features single photon counting, comprises a preamplifier, a comparator and a counter. The preamplifier enforces the charge generated in the sensor by the incoming x-ray; the comparator produces a digital signal if the incoming charge exceeds a predefined threshold and thus, together with the counter, one obtains a complete digital storage and read-out of the number of detected x-rays per pixel without any read-out noise or dark current! PILATUS detectors feature several advantages compared to current state-of-the-art CCD and imaging plate detectors. The main features include: no readout noise, superior signal-to-noise ratio, read-out time of 5 ms, a dynamic range of 20bit, high detective quantum efficiency and the possibility to suppress fluorescence by a energy threshold that is set individually for each pixel. A more complete comparison is given in Table 1. The short readout and fast framing time allow to take diffraction data in continuous mode without opening and closing the shutter for each frame (see Fig. 1). For a comparison on the response to x-rays of integrating and single photon counting detectors see Fig. 2. Because of the specified properties, PILATUS detectors are superiour to state-of-the-art CCD and imaging plate detectors for various x-ray detection experiments. Major improvements can be expected for time-resolved experiments, for the study of weak diffraction phenomena (e.g. diffuse scattering), for accurate measurements of Bragg intensities, for resonant scattering experiments,...
PILATUS Detector SystemsThe PILATUS chip was designed in 2004 at the PSI and is fabricated in the UMC 0.25 radiation hard design. Each chip contains an array of 60 x 97 pixels with a pixel size of 0.172 mm. The active area spans 10 x 17 mm2. Each pixel contains a charge-sensitive preamplifier and shaper, a single-level comparator with a 6-bit individual threshold adjustment, a 20-bit counter with a count rate of ~1.5 MHz/pixel/s. The PILATUS modules consists of a Hamamatsu sensor bump-bonded to an array of 8 x 2 chips using indium balls. The 16 chips of a module are read out in parallel within a read-out time of ~2 ms. The quality of the modules is very high, less than 0.005% dead pixels are routinely achieved during module production. At present, three PILATUS detecor systems are available or in construction. The PILATUS 100K detector consists of a single module and has 487 x 195 pixels with a pixel size of 0.172 mm. The active area spans over 84 x 34 mm2. Such a detector is in use at the X04SA materials science beamline at the SLS for surface diffraction experiments since 2006.
Prototypes: First Generation PILATUS Detector SystemsThe first generation PILATUS chip was designed in 2000 at the PSI and fabricated in the DMILL radiation tolerant CMOS process (Atmel Temic SA, Nantes, France). Each chip contains an array of 44 x 78 pixels with a pixel size of 0.217 mm. The active area spans 10 x 17 mm2. Each pixel contains a charge-sensitive preamplifier and shaper, a single-level comparator with a 4-bit individual threshold adjustment, a 15-bit counter with a clock frequency of 10 kHz. The PILATUS module consists of a single, fully depleted silicon sensor (Colybris SA, Neuchatel, Switzerland) bump-bonded to an array of 8 x 2 chips using indium balls. The sensor is a continuous array of 366 x 157 pixels without dead areas. Double-sized pixels are used at the chip boundaries to span the gap between neighbouring chips. The 16 chips of a module are read out in parallel at a clock frequency of 10 MHz, which leads to a read out time of 6.7 ms for one module. The PILATUS 1M detector consists of 6 banks, each containing 3 modules in a row with a total of 1120 x 967 pixels. The banks are tilted by 6º with respect to the mounting frame and the modules overlap in the vertical direction in order to reduce the dead area. The read-out of all 18 modules is done in parallel within 6.7 ms with a count rate of 10 kHz.
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